Random access memory integrated circuits (RAM IC's) undergo testing by the manufacturer during production and by the end user, for example, in a memory test conducted during computer initialization. As RAM IC densities increase, so that individual RAM IC's are capable of storing four or more megabits of information, the time necessary for testing the IC's increases as well. To reduce the testing time required, it is known to place the RAM IC's in a test mode for that purpose, as distinguished from the normal operating mode. In a normal operating mode, a RAM IC reads and writes one bit or word at a time. A RAM IC could be tested in the normal operating mode but the time required to conduct exhaustive testing is excessive.
In a test mode, multiple bits or words in the RAM IC are tested simultaneously, thus reducing test time. In a four megabit DRAM, for example, Toshiba, part no. TC514100J/Z, the RAM is organized 4,194,304 words by one bit, and is internally organized as 524,288 words by eight bits. In test mode, data are written into eight sectors in parallel and retrieved in the same way. Three of the address lines are not used. If, upon reading, all bits are equal (all ones or zeros), the data output pin indicates a one. If any of the bits differed, the data output pin would indicate a zero. In test mode, therefore, the 4M DRAM can be tested as if it were a 512K DRAM, thereby reducing the testing time.
Switching a RAM IC into test mode can be accomplished by using a combination of input signals that would not be encountered in normal operation. For example, the Toshiba 4M DRAM mentioned above is switched into test mode by inserting WRITE* and CAS* signals before RAS* cycle (where an asterisk indicates a complement or active low signal). Input signal CAS* before RAS* refresh cycle or RAS* only refresh cycle returns the device to the normal operating mode.
It is also known to switch a RAM IC device into test mode by using a supervoltage technique. A test function voltage is applied to one of the IC pins (typically called TE, or test mode enable), to trigger the device into a test mode. A typical test function voltage is 4.5 volts higher than the chip supply voltage (Vcc).
As integrated circuit fabrication processes evolve to ever smaller geometries, however, it is fast becoming necessary to lower the test function voltage to a voltage that is closer to the normal signal level voltage. Very small geometry devices cannot withstand the supervoltage levels used in the past, without taking special steps to avoid leakage. However, if the test function voltage is lowered too much, there is a risk that the IC will inadvertently be triggered into test mode by signal noise normally incident in high speed circuitry and wiring. In other words, the noise margin with respect to test mode triggering is compromised.
The need remains, therefore, for a simple and reliable way to switch a RAM IC into a test mode without subjecting the device to excessive supervoltage signals, and while maintaining adequate noise immunity.